1. Field of the Invention
The present invention generally relates to a semiconductor memory device and, more particularly, to a semiconductor memory device for inputting and outputting data in synchronization with an external clock signal.
2. Description of the Related Art
Recently, a Dynamic Random Access Memory (DRAM) has been facing requirements, such as to operate at high speed, to consume less electric power, and to have a high-speed interface. In this trend, a Synchronized DRAM (SDRAM) is a mainstream type of the DRAM, the SDRAM inputting and outputting data in synchronization with a clock signal. Even a DDR (Double Data Rate) type is proposed to enhance an interface speed This DDR type outputs data by using a clock signal CK and a reverse clock signal /CK so as to increase an output rate. In any type of the DRAM, an operating frequency has to be increased so as to achieve a high-speed interface.
However, when a high-frequency clock signal controls an internal operation, a margin in a specification becomes smaller as the frequency of the clock signal becomes higher, making it difficult to guarantee a reliability of the internal operation. Therefore, an operating frequency of the internal operation has to be decreased by such method as a frequency dividing.
The above-mentioned decrease in an operating frequency is especially employed in controlling a data output. Hereinafter, a description will be given, with reference to the drawings, of a conventional semiconductor memory device having this function.
FIG. 1 is an illustration of a structure of a conventional semiconductor memory device. As shown in FIG. 1, the conventional semiconductor memory device comprises: pads 1, 3, 5 and 33; clock buffers 7 and 8; a command buffer 9; a frequency divider 11; a command recognition unit 13; a DLL (Delayed Locked Loop) circuit 15; an output signal generating circuit 17; a 0xc2x0 logic circuit 19; a 180xc2x0 logic circuit 21; an output control unit 23; a readout circuit 25; a memory 27; a data control unit 29; and an output buffer 31. The 0xc2x0 logic circuit 19 includes a read-command angle recognition circuit (0xc2x0) 35 and a counter (0xc2x0) 39. The 180xc2x0 logic circuit 21 includes a read-command angle recognition circuit (180xc2x0) 37 and a counter (180xc2x0) 41.
Each of the clock buffers 7 and 8 is connected to the pads 1 and 3, the pad 1 supplied with an external clock signal ck, and the pad 3 supplied with an external clock signal/ck. The command buffer 9 is connected to the pad 5 supplied with a command com. The frequency divider 11 is connected to the clock buffers 7 and 8. The command recognition unit 13 is connected to the clock buffer 7 and the command buffer 9. The DLL circuit 15 is connected to the frequency divider 11.
The output signal generating circuit 17 is connected to the DLL circuit 15. Each of the 0xc2x0 logic circuit 19 and the 180xc2x0 logic circuit 21 is connected to the frequency divider 11, the command recognition unit 13 and the DLL circuit 15. The output control unit 23 is connected to the 0xc2x0 logic circuit 19 and the 180xc2x0 logic circuit 21. The readout circuit 25 is connected to the command recognition unit 13. The memory 27 is connected to the readout circuit 25. The data control unit 29 is connected to the readout circuit 25 and the output control unit 23. The output buffer 31 is connected to the data control unit 29 and the output signal generating circuit 17. The pad 33 outputting data D is connected to the output buffer 31.
Hereinafter, a description will be given, with reference to the drawings, of operations of the conventional semiconductor memory device having the above-mentioned structure. The external clock signal ck supplied to the pad 1 and the external clock signal /ck supplied to the pad 3 are buffered by the clock buffers 7 and 8, and are supplied to the frequency divider 11 as an internal clock signal clkz from the clock buffer 7 and an internal clock signal clkx from the clock buffer 8. Then, the frequency divider 11 divides frequencies of the internal clock signals clkz and clkx so as to generate internal clock signals clke0z, clke18z, clko0z and clko18z.
On the other hand, the command com supplied to the pad 5 is buffered by the command buffer 9, and is supplied to the command recognition unit 13. Then, the command recognition unit 13 generates a read-command read and supplies the read-command read to the read-command angle recognition circuit (0xc2x0) 35, the read-command angle recognition circuit (180xc2x0) 37 and the readout circuit 25. The read-command angle recognition circuit (0xc2x0) 35 detects whether the read-command read is supplied in synchronization with the internal clock signal clke0z, and supplies an output control signal to the output control unit 23. The read-command angle recognition circuit (180xc2x0) 37 detects whether the read-command read is supplied in synchronization with the internal clock signal clke18z, and supplies an output control signal to the output control unit 23. In this course, a phase of the internal clock signal clke18z is different to a phase of the internal clock signal clke0z by 180xc2x0.
The DLL circuit 15 delays the internal clock signals clke0z, clke18z, clko0z and clko18z generated by the frequency divider 11 by a predetermined time so as to generate internal clock signals oclke0z, oclke18z, oclko0z and oclko18z which seem as if being a transmission time TAC ahead of the internal clock signals clke0z, clke18z, clko0z and clko18z in phases, the transmission time TAC corresponding to a path 43 from the DLL circuit 15 to the pad 33.
Hereinafter, a description will be given, with reference to FIG. 2, of data-read operations of the conventional semiconductor memory device shown in FIG. 1. FIG. 2 is a waveform diagram indicating operations of the conventional semiconductor memory device. The description will be made of a case where a latency is six. That is, as indicated by FIG. 2-(a) and FIG. 2-(m), data Dn (n is a natural number) are output from the pad 33 at a time To which is six periods (clocks) of the external clock signal ck behind a time Ti at which a read-command read is supplied to the pad 5.
First, as shown by waveforms 46 indicated by FIG. 2-(b) to FIG. 2-(e), the internal clock signals clke0z, clke18z, clko0z and clko18z are generated by the frequency divider 11 dividing by two the frequencies of the internal clock signals clkz and clkx based on the external clock signal ck. Waveforms 44 indicate the internal clock signals clke0z and clke18z being in synchronization with the external clock signal ck. Waveforms 45 indicate the internal clock signals clko0z and clko18z in being synchronization with the external clock signal /ck reverse to the external clock signal ck. The internal clock signals clke18z and clko18z are different in phases to the internal clock signals clke0z and clko0z by 180xc2x0, respectively.
Therefore, as indicated by FIG. 2-(b) and FIG. 2-(c), the internal clock signal clke0z, for example, comprises only even-numbered clocks of the external clock signal ck, and the internal clock signal clke18z, for example, comprises only odd-numbered clocks of the external clock signal ck.
Waveforms 47 indicate the signals delayed by the DLL circuit 15 Waveforms 48 correspond to the waveforms 44, and waveforms 49 correspond to the waveforms 45. That is, a clock numbered 4 of the internal clock signal clke0z indicated by FIG. 2-(b), for example, is delayed by the DLL circuit 15 by a predetermined time to become a clock numbered 6 of the internal clock signal oclke0z indicated by FIG. 2-(f).
On the other hand, the read-command angle recognition circuit (0xc2x0) 35 recognizes a reception of the read-command read with a phase difference 0xc2x0 to the external clock signal ck based on the supplied internal clock signal clke0z so as to generate a signal ractp0z indicated by FIG. 2-(j). This signal ractp0z is at a high level for one period of the supplied internal clock signal clke0z, and is supplied to the counter (0xc2x0) 39. It is noted that the read-command angle recognition circuit (180xc2x0) 37 recognizes a reception of the read-command read with a phase difference 180xc2x0 to the external clock signal ck based on the supplied internal clock signal clke18z so as to operate in the same manner as the above-mentioned read-command angle recognition circuit (0) 35.
Then, the counter (0) 39 generates signals latz and oe0z indicated by FIG. 2-(k) and FIG. 2-(l) one by one in response to the internal clock signals oclko0z and oclko18z supplied from the DLL circuit 15. Then, from the time To, in response to the clocks numbered 6 and after of the internal clock signal oclke0z indicated by FIG. 2-(f), data D1 to D4 with the latency of 6 are supplied via the data control unit 29 to the output buffer 31 and are output from the pad 33 one by one.
The readout circuit 25 reads the above-mentioned data D1 to D4 from the memory 27 in response to the read-command read, and supplies the data D1 to D4 to the data control unit 29. The data control unit 29 supplies the data D1 to D4 to the output buffer 31 in response to a data control signal supplied from the output control unit 23. The output buffer 31 supplies the data D1 to D4 to the pad 33 in response to signals outp1x and outp2x supplied from the output signal generating circuit 17.
The heretofore mentioned is the description of data-read operations of the conventional semiconductor memory device shown in FIG. 1. Hereinafter, descriptions will be given of specific circuit examples of elements composing the conventional semiconductor memory device shown in FIG. 1.
FIG. 3 is an illustration of a structure of the DLL circuit 15 shown in FIG. 1. As shown in FIG. 3, the DLL circuit 15 comprises a replica circuit 90, a first delay circuit 91, a second delay circuit 92, a shift register 93, a xc2xd frequency dividing circuit 94, and a phase comparator 55. The first delay circuit 91 and the second delay circuit 92 have the same circuit structure. The replica circuit 90 comprises a resistance 95, an output buffer (dummy) 96, a dummy capacitance 97, a clock buffer (dummy) 98, and a dummy frequency divider 99, these elements being connected in series in this order. The dummy frequency divider 99 comprises a circuit having a same delay time as the frequency divider 11 shown in FIG. 1, and supplies a supplied signal to the phase comparator 55 without dividing a frequency thereof.
The xc2xd frequency dividing circuit 94 is supplied with the internal clock signal clke0z. The phase comparator 55 is connected to the xc2xd frequency dividing circuit 94 and the dummy frequency divider 99. An input terminal of the shift register 93 is connected to the phase comparator 55, and the shift register 93 controls the second delay circuit 92. An input terminal of the second delay circuit 92 is connected to the xc2xd frequency dividing circuit 94, and an output terminal of the second delay circuit 92 is connected to the resistance 95. The second delay circuit 92 adjusts a delay time in the first delay circuit 91 so that the delay time in the first delay circuit 91 matches a delay time in the second delay circuit 92.
Here, the first delay circuit 91 is supplied with the internal clock signals clke0z, clke18z, clko0z and clko18z, and generates and outputs the internal clock signals oclke0z, oclke18z, oclko0z and oclko18z delayed by the same time as the delay time of the second delay circuit 92. Additionally, the above-mentioned replica circuit 90 has the same delay time as an xe2x80x9cinternal clock pathxe2x80x9d, which is a path from the clock buffers 7 and 8 via the first delay circuit 91 to the output buffer 31, because the replica circuit 90 has the same structure of circuits as the xe2x80x9cinternal clock pathxe2x80x9d.
Next, a description will be given of operations of the above-mentioned DLL circuit 15. An optimal number of delay stages in the first and second delay circuits 91 and 92 is specified by the shift register 93. The shift register 93 is controlled by the phase comparator 55. The phase comparator 55 compares a dummy clock signal clkr supplied from the replica circuit 90 and a clock signal clkout supplied from the xc2xd frequency dividing circuit 94, and controls the shift register 93 so that a phase of the dummy clock signal clkr is delayed from a phase of the clock signal clkout by one period of the internal clock signal clke0z. Thereby, the delay time in the xe2x80x9cinternal clock pathxe2x80x9d becomes a time equivalent to one period of the internal clock signal clke0z. Therefore, output data are varied at rise times of the external clock signal ck, regardless of a frequency of the external clock signal ck.
It is noted that the xc2xd frequency dividing circuit 94 has a frequency division rate of 2 so that the phase comparator 55 conducts the above-mentioned phase comparison based on a clock one clock behind the corresponding clock of the signals supplied to the first delay circuit 91.
Hereinbelow, a more detailed description will be given, with reference to FIG. 4, of operations of the above-mentioned DLL circuit 15. FIG. 4 is a waveform diagram indicating the operations of the DLL circuit 15. It is noted that, in this description, data is output at the time To.
First, the external clock signal ck indicated by FIG. 4-(a) supplied to the pad 1 is frequency-divided by the frequency divider 11 shown in FIG. 1 so that the internal clock signal clke0z indicated by FIG. 4-(B) is generated. It is noted that, as indicated by FIG. 4-(a) and FIG. 4-(b), clocks of the external clock signal ck are numbered with sequential integers from 0, and clocks of the generated internal clock signal clke0z are numbered with the same numbers, i.e., the even numbers, as the clocks of the external clock signal ck having the same rise time.
Then, a frequency of the internal clock signal clke0z is divided by 2 in the xc2xd frequency dividing circuit 94 so that the clock signal clkout indicated by FIG. 4-(c) is generated. Then, this clock signal clkout is transmitted through the second delay circuit 92 and the replica circuit 90 so that the dummy clock signal clkr indicated by FIG. 4-(d) is generated. As indicated by FIG. 4-(d), a phase of the dummy clock signal clkr is delayed from a phase of the clock signal clkout by a delay time Dt in the replica circuit 90.
At the time To, the phase comparator 55 controls the shift register 93 so that a rising edge of the dummy clock signal clkr matches a falling edge of the clock signal clkout. Thereby, the delay time in the second delay circuit 92 and the first delay circuit 91 is made a time from a time T3 to the time To. Therefore, as indicated by FIG. 4-(e), the internal clock signal oclke0z output from the first delay circuit 91 is delayed from the internal clock signal clke0z supplied to the first delay circuit 91 by a time from a time T1 to a time T2, which is the same time as the time from the time T3 to the time To. For example, as indicated by FIG. 4-(e), a clock numbered 4 of the internal clock signal oclke0z corresponds to a clock numbered 2 of the internal clock signal clke0z.
Then, as indicated by FIG. 4-(f), at the time To, data is output from the pad 33 in response to the clock numbered 4 of the internal clock signal oclke0z. As a result, the data is output in synchronization with a clock numbered 4 of the external clock signal ck indicated by FIG. 4-(a).
The above-described operations of the DLL circuit 15 shown in FIG. 3 are characterized in that the phase of the dummy clock signal clkr supplied from the replica circuit 90 is adjusted to an edge of the clock signal clkout supplied from the xc2xd frequency dividing circuit 94, the edge corresponding to a clock one period behind of the internal clock signal clke0z supplied to the first delay circuit 91.
Next, a description will be given, with reference to FIG. 5, of the above-mentioned conventional clock buffer 7. FIG. 5 is a circuit diagram of the conventional clock buffer 7 shown in FIG. 1. It is noted that the clock buffer 8 shown in FIG. 1 has the same structure as shown in FIG. 5.
As shown in FIG. 5, the clock buffer 7 includes inverters INV1 to INV3, N-channel MOS transistors NT1 To NT3, and P-channel MOS transistors PT1 to PT4. The external clock signal ck is supplied to a gate of the N-channel MOS transistor NT2. The external clock signal /ck is supplied to a gate of the N-channel MOS transistor NT3. An enable signal enz is supplied to gates of the N-channel MOS transistor NT1 and the P-channel MOS transistors PT1 and PT4.
When the enable signal enz becomes high-level so that the clock buffer 7 is activated, the internal clock signal clkz according to the external clock signals ck and /ck is generated and is output.
FIG. 6 is a circuit diagram of the conventional frequency divider 11 shown in FIG. 1. As shown in FIG. 6, the frequency divider 11 includes an inverter INV4, a first frequency dividing circuit 11a and a second frequency dividing circuit 11b. The first frequency dividing circuit 11a includes NAND circuits 100 to 108 and an inverter INV5. The second frequency dividing circuit 11b includes NAND circuits 109 to 117 and an inverter INV6.
The first frequency dividing circuit 11a frequency-divides the internal clock signal clkz so as to generate the internal clock signals clke0z and clke18z. The second frequency dividing circuit 11b frequency-divides the internal clock signal clkx so as to generate the internal clock signals clko0z and clko18z. It is noted that the frequency divider 11 is reset by a signal csuz supplied to the inverter INV4.
The heretofore-described conventional semiconductor memory device employs the DDR mode, in which a plurality of external clock signals ck and /ck control a data output. However, the conventional semiconductor memory device of the DDR mode has a disadvantage of involving complicated controls thereof. Additionally, since a plurality of internal clock signals having different phases are generated by frequency-dividing the external clock signals, a number of signal lines is increased so as to transmit the internal clock signals, subsequently augmenting a circuit scale of the DLL circuit 15 and an amount of consumed electric current thereof. Further, the augmented circuit scale of the DLL circuit 15 disadvantageously leads to differences in quality of the signal lines in the DLL circuit 15, deteriorating a precision of the DLL circuit 15.
It is a general object of the present invention to provide an improved and useful semiconductor memory device in which device the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide a semiconductor memory device which can operate with excellent reliability even at high operating frequencies, the device having a reduced circuit scale and consuming a decreased amount of electric current.
In order to achieve the above-mentioned objects, there is provided according to one aspect of the present invention a semiconductor memory device for outputting data in synchronization with an external clock signal, the device comprising:
a first frequency divider dividing a frequency of the external clock signal supplied thereto so as to generate a first internal clock signal;
a delay circuit delaying the external clock signal;
a second frequency divider dividing a frequency of a signal supplied from the delay circuit so as to generate a second internal clock signal; and
a data control unit outputting the data according to the first internal clock signal and the second internal clock signal.
According to the present invention, even when the frequency of the external clock signal is high, an internal operating frequency can be reduced so as to output data from the data control unit in synchronization with the external clock signal, and at the same time, a number of signals supplied to the delay circuit can be decreased.
Additionally, in the semiconductor memory device according to the present invention, the delay circuit supplies a signal having a phase different from a phase of the external clock signal by N periods, where N is an integer other than zero.
According to the present invention, the first frequency divider and the second frequency divider can be synchronized with each other.
Additionally, in the semiconductor memory device according to the present invention, the delay circuit adjusts a phase of the external clock signal supplied thereto by delaying the external clock signal by 2n periods, where n is a natural number.
According to the present invention, the first frequency divider and the second frequency divider can be synchronized with each other easily.
Additionally, the semiconductor memory device according to the present invention may further comprise a reset circuit simultaneously starting the first frequency divider and the second frequency divider.
According to the present invention, operations of the first frequency divider and the second frequency divider can be guaranteed.
Specifically, in the semiconductor memory device according to the present invention, the reset circuit starts the first frequency divider and the second frequency divider upon being provided with a power supply.
According to the present invention, operations of the first frequency divider and the second frequency divider can be surely guaranteed.
Additionally, in the semiconductor memory device according to the present invention, the reset circuit may be controlled by a command supplied from outside.
According to the present invention, operations of the first frequency divider and the second frequency divider can have an enhanced degree of freedom.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention a semiconductor memory device having a clock buffer buffering an external clock signal supplied thereto, and a data control unit outputting predetermined data according to a data control signal supplied thereto, the device outputting the data in synchronization with the external clock signal, the device comprising:
a delay circuit delaying a signal generated by the clock buffer;
a first frequency divider dividing a frequency of the signal generated by the clock buffer so as to generate a first internal clock signal;
a second frequency divider dividing a frequency of a signal supplied from the delay circuit so as to generate a second internal clock signal; and
an output control unit generating the data control signal according to the first internal clock signal and the second internal clock signal.
According to the present invention, even when the frequency of the external clock signal is high, the data control signal generated according to the first internal clock signal and the second internal clock signal each having a decreased frequency enables the data output from the data control unit in synchronization with the external clock signal, and a number of signals supplied to the delay circuit can be reduced.